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[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other resource] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98080 | Author: lhxmodelsim | Hits:

[Other resource] SDR_4Mx16_HY57V641620HG_verilogl

Description: Hynix公司8M byte sdr sdram的verilog语言仿真实现。
Platform: | Size: 105911 | Author: 张力 | Hits:

[Other resource] H1wQqGvI

Description: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL
Platform: | Size: 777515 | Author: 黄辉辉 | Hits:

[Other resource] SDRAM

Description: ALTERA SDR AM Controller White Paper
Platform: | Size: 658903 | Author: 付茗 | Hits:

[Other resource] FPGA_SDR_Sdram_LED

Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。
Platform: | Size: 511642 | Author: 郑宏超 | Hits:

[Other] ref-sdr-sdram-verilog

Description: sdram控制器的开发程序，还有文档，可以参考以下
Platform: | Size: 776866 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] Xilinx公司网站下的SDRAM Controller的参考设计

Description:
Platform: | Size: 128000 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[MiddleWare] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98304 | Author: | Hits:

[Software Engineering] FPGA_SDR_Sdram_LED

Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。-For the main control board memory (SRAM) a small amount of stored data and the highest frequency of low, based on SDR Sdram (Synchronous Dynamic RAM) as the main memory of the LED display systems. In the experiment, the use of field programmable gate array (FPGA) to realize the logic function of each module. The eventual realization of L ED display control, and a master control panel to maximize the control of the 256 × 128 pixels point, based on the same conditions than the static memory control area has doubled, to verify the dynamic memory of nuclear [7 ] the practicality.
Platform: | Size: 510976 | Author: 郑宏超 | Hits:

[ARM-PowerPC-ColdFire-MIPS] TEST

Description: S3c2440硬件测试程序，主要功能包括：SDRAM读写测试，整片Falsh读写测试，Flash擦除，坏块检测，flash复制数据到SDRAM-S3c2440 hardware testing procedures, the main features include: SDRAM read and write tests, reading and writing test Falsh whole, Flash erase bad block detection, flash copy the data to the SDRAM
Platform: | Size: 502784 | Author: 冯健 | Hits:

[VHDL-FPGA-Verilog] SDRAM_VerilogCode

Description: 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
Platform: | Size: 26624 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] WRCTRL

Description: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block
Platform: | Size: 2048 | Author: Taher Aghazadeh | Hits:

[Program doc] SDRAM

Description: TMS320C6713 跟SDRAM 溝通程式-Connect SDRAM program for TMS320C6713
Platform: | Size: 384000 | Author: 許好險 | Hits:

[Software Engineering] SDRAM

Description: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Platform: | Size: 1903616 | Author: luyi | Hits:

[Software Engineering] HOW_TO_USE_SDRAM

Description: HOW TO USE SDRAM？尔必达的技术文档，详细阐述了SDRAM内存的控制原理，绝对值得研读和收藏！-HOW TO USE SDRAM? Elpida technical documentation described in detail SDRAM memory, control theory, definitely worth reading and collecting!
Platform: | Size: 344064 | Author: 方伟 | Hits:

[VHDL-FPGA-Verilog] SDR-SDRAMverilog

Description: 经典三星SDR SDRAM读写verilog代码分享-Classic Samsung SDR SDRAM read and write verilog code share
Platform: | Size: 4056064 | Author: liuxiaoyu | Hits:

[Other] sdr-sdram-verilog

Description: SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Platform: | Size: 1277952 | Author: wushj | Hits:

[VHDL-FPGA-Verilog] SDR-SDRM

Description: 该工程对三星SDR SDRAM（K4S641632）进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等-The project of Samsung SDR SDRAM (K4S641632), read and write, internal engineering points for PLL and reset processing module, SDRAM logic module, SDRAM logic module read SDRAM read and write encapsulation module, read and write cache FIFO module, serial occurrence module
Platform: | Size: 10430464 | Author: 陈超 | Hits:
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